The present invention relates to a magnetic random access memory (hereinafter MRAM) having a vertical structure transistor and, more particularly, to a MRAM having a faster access time than SRAM, a high density like that of DRAM, and a non-volatility like a flash memory device.
As one of the next generation memory devices, MRAMs using a ferromagnetic material have been proposed by some semiconductor memory manufacturing companies. The MRAM is a memory device for reading and writing information that relies upon forming multi-layer ferromagnetic thin films and sensing current variations that depend upon the magnetization direction of the respective thin films. The MRAM device offers a high speed and low power consumption, and it allows for high integration density because of the special properties of the magnetic thin film. It also performs a nonvolatile memory operation, like a flash memory device.
Memory storage in a MRAM is achieved by using a giant magneto-resistive (abbreviated as xe2x80x98GMRxe2x80x99) phenomenon or a spin-polarized magneto-transmission (SPMT) in which spin influences electron transmission. GMR devices rely upon the variation in resistance that occurs when spin directions for two magnetic layers, having a non-magnetic layer therebetween, are different.
The SPMT technique utilizes the phenomenon that larger currents are transmitted when spin directions are identical in two magnetic layers, having an insulating layer therebetween. This is used to create a magnetic permeable junction memory device.
Despite these techniques, the MRAM research is still in its early stages, and mostly concentrated on the formation of multi-layer magnetic thin films. Little research is performed on unit cell structure or the peripheral sensing circuit.
FIG. 1 is a cross-sectional diagram illustrating a conventional MRAM. Shown is a gate electrode 33, i.e., a first word line, that has been formed on a semiconductor substrate 31. Source/drain junction regions 35a and 35b are formed on the semiconductor substrate 31 on both sides of the first word line 33, respectively. A ground line 37a and a first conductive layer 37b are formed to contact the source/drain junction regions 35a and 35b, respectively. Here, the ground line 37a is formed during the patterning process that forms the first conductive layer 37b. Thereafter, a first interlayer insulating film 39 is formed to planarize the whole surface of the resultant structure, and a first contact plug 41 is formed to contact the first conductive layer 37b, through the first interlayer insulating film 39.
A second conductive layer, which is a lower read layer 43 contacting the first contact plug 41, is patterned. A second interlayer insulating film 45 is formed to planarize the whole surface of the resultant structure, and a second word line, which is a write line 47, is formed on the second interlayer insulating film 45. A third interlayer insulating film 48 is formed to planarize the upper portion of the second word line 47.
A second contact plug 49 is formed to contact the second conductive layer 43. A seed layer 51 is formed to contact the second contact plug 49. Here, the seed layer 51 is formed to overlap between the upper portion of the second contact plug 49 and the upper portion of the write line 47. Then, a fourth interlayer insulation layer 53 is formed and planarized to expose the seed layer 51. Thereafter, a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer 55, a tunnel junction layer 57, and a free ferromagnetic layer 59 are stacked on the seed layer 51, thereby forming a magnetic tunnel junction (MTJ) cell 100 having a pattern size as large as the write line 47 and overlapping the write line 47 in location.
At this time, the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer 55 from changing, and the magnetization direction of the tunnel junction layer 57 is fixed to one direction. The magnetization direction of the free ferromagnetic layer 59 can be changed by application of an external magnetic field, and a xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 bit can be stored by the device according to the magnetization direction of the free ferromagnetic layer 59. A fifth interlayer insulation layer 60 is formed on the whole surface and planarized to expose the free ferromagnetic layer 59, and an upper read layer, i.e., bit line 61 connected to free ferromagnetic layer 59 is formed.
In operation, the unit cell of the MRAM includes one field effect transistor formed of the first word line 33, which is a read line used to read information, the MTJ cell 100, and the second word line 47. The second word line 47 is a write line that determines the magnetization direction of the MTJ cell 100 by applying a current to form an external magnetic field. The field effect transistor also includes the bit line 61, which is an upper read layer for determining the magnetization direction of the free ferromagnetic layer 59 by applying a current to the MTJ cell 100 that flows in a vertical direction.
To read the information from the MTJ cell 100, a voltage is applied to the first word line 33, as the read line. This turns the field effect transistor on, and, by sensing the magnitude of the current applied to the bit line 61, the magnetization direction of the free ferromagnetic layer 59 in the MTJ cell 100 is detected and its state read.
During storage of information in the MTJ cell 100, the field effect transistor is in an off state and the magnetization direction in the free ferromagnetic layer 59 is controlled by a magnetic field generated by applying current to the second word line 47, which is the write line, and to the bit line 61. When current is applied to the bit line 61 and the write line 47 at the same time, the generated magnetic field is strongest at a vertical intersecting point of the two metal lines. This may be used to select one cell from a plurality of cells, for example.
The operation of the MTJ cell 100 in the MRAM will now be described. When the current flows in the MTJ cell 100 in a vertical direction, a tunneling current flows through an interlayer insulating film. When the tunnel junction layer 57 and the free ferromagnetic layer 59 have the same magnetization direction, this tunneling current increases. When the tunnel junction layer 57 and the free ferromagnetic layer 59 have different magnetization directions, however, the tunneling current decreases due to a tunneling magneto resistance (TMR) effect. A decrease in the magnitude of the tunneling current due to the TMR effect is sensed, and, thus, the magnetization direction of the free ferromagnetic layer 59 is sensed, which thereby detects the information stored in the MTJ cell 100.
As described above, the conventional MRAM comprises a horizontal structure transistor having the write line as the second word line and the MTJ cell in a vertical stack on an upper portion of the transistor. In order to form the MRAM, surface roughness in the lower part of the device, where the MTJ cell is formed, should be controlled within nanometer tolerances. However, since there is a second word line and contact lines below the MTJ cell it is difficult to prevent surface roughness on the lower part of the device to within nanometer ranges.
Since the structure of a MRAM device is more complex than that of DRAM, as a whole, the MRAM requires a total of four metal lines per unit cell, i.e., two word lines, one bit line, and a ground line. MRAMs using the MTJ cell could potentially offer high integration, i.e., integration on the order of several to 100 gigabits To achieve this, increasing a short channel effect of a transistor and control of resistance are important factors. However, the resistance is more difficult to control as the size of the transistor becomes smaller, and the resistance of the transistor together with that of the MTJ cell has a great influence on cell operations.
According to an embodiment, a magnetic random access memory comprises a vertical structure transistor; a read line connected to a gate electrode formed at a sidewall of the vertical structure transistor; a magnetic tunnel junction cell formed on a drain junction region existing over an upper portion of the vertical structure transistor; and a write line formed on an upper portion of the magnetic tunnel junction cell.
The MRAM also comprises a vertical structure transistor; a first word line connected to a gate electrode of the vertical structure transistor; a contact line connected to the vertical structure transistor; a MTJ cell formed on the contact line; a bit line formed on the MTJ cell; and a second word line formed on the bit line over an upper portion of MTJ cell. Another embodiment provides a method for forming the MRAM comprises the steps of: etching a semiconductor substrate by photolithography using an active mask to form a circular pillar; forming a gate oxide layer at sidewalls of the circular pillar; performing ion implantation of a high concentration impurity on the substrate and on a top portion of the circular pillar by a drive-in process, thereby forming a drain junction region on the upper side of the circular pillar and a source junction region on the bottom of the circular pillar extending into the substrate surface; forming a first word line of a gate electrode by forming a planarized conductor layer for the gate electrode exposing the drain junction region and then patterning the planarized conductor layer; forming a planarized first interlayer insulation layer; forming a contact line contacting the drain junction region through the first interlayer insulation layer; forming a semi-magnetic layer, a pinned ferromagnetic layer, a tunnel junction layer, and a free ferromagnetic layer above the contact line; forming a magnetic tunnel junction cell by patterning the semi-magnetic layer, the pinned ferromagnetic layer, the tunnel junction layer, and the free ferromagnetic layer by photolithography using a magnetic tunnel junction cell mask; forming a planarized second interlayer insulation layer exposing the magnetic tunnel junction cell; forming a bit line contacting the free ferromagnetic layer; and forming a second word line over the magnetic tunnel junction cell and above the bit line.
Yet, another embodiment provides method for forming the MRAM comprising the steps of: etching a semiconductor substrate by photolithography using an active mask, thereby forming a circular pillar extending above the substrate; forming a gate oxide layer on the substrate; performing an ion implantation of a high concentration impurity and drive-in processes, thereby forming a drain junction region on an upper portion of the circular pillar and a source junction region on a bottom portion of the circular pillar and on the substrate; forming a conductor layer for a gate electrode at a predetermined thickness on the substrate, and performing an anisotropic etching process, thereby forming a gate electrode in the form of a conductor spacer at a sidewall of the circular pillar; forming a planarized first interlayer insulation layer; forming a contact line contacting the drain junction region through the first interlayer insulation layer; forming a semi-magnetic layer, a pinned ferromagnetic layer, a tunnel junction layer, and a free ferromagnetic layer above the contact line; forming the magnetic tunnel junction cell by pattering the semi-magnetic layer, the pinned ferromagnetic layer, the tunnel junction layer, and the free ferromagnetic layer by photolithography using a magnetic tunnel junction cell mask; forming a planarized second interlayer insulator exposing the magnetic tunnel junction cell; forming a bit line contacting the free ferromagnetic layer; and forming a second word line over an upper portion of the magnetic tunnel junction cell and above the bit line.